I. Multi-Gate-Fingers NMOSFET and the Issue:
An NMOSFET is a very effective ESD protection device. In one application, with the gate connected to a gate-driving signal, the NMOSFET is used as the pull down device of a CMOS buffer to drive an output voltage. In a second application, with the gate electrically connected to the ground, the NMOSFET is used to protect an input pin or power bus during an ESD event.
In a PS (Positive-Voltage-to-VSS) mode ESD event, a positive ESD transient voltage applied to an IC pin while a VSS power pin is at ground potential, the protection of an NMOSFET heavily depends on the snap-back mechanism for conducting large amount of ESD current between the drain and source. To start, the high electric field at the drain junction causes impact ionization, which generates both minority and majority carriers. The minority carriers flow toward the drain contact and the majority carriers flow toward the substrate/pwell contact causing a local potential build up in the current path in pwell. When the local substrate potential is 0.6V higher than the adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction injects minority carriers (electrons) into the pwell, and those carriers eventually reach the drain junction to further enhance the impact ionization (see Ref. 1b). And as a continuous loop the MOSFET gets into a low impedance (snap back) state to conduct large amount of ESD current.
In a multi-finger NMOS structure as shown in FIG. 1A and FIG. 1B, not all gate fingers may turn on during an ESD event. This is because the first few gate finger having turned on quickly get into a snap-back low-impedance condition. It reduces the drain terminal 11 to source terminal 12 voltage to a transient voltage less than the trigger voltage of the NMOS device. This potentially prevents other gate fingers from turning on. Therefore, with only partial number of gate fingers turned on to absorb the ESD energy, the size of the NMOSFET is effectively reduced and the ESD performance degrades.
When a gate finger is triggered in an ESD event, the entire finger turns on. This is due to a cascading effect that a local source junction in a forward biasing state will inject lots of carriers into the substrate to flow toward the drain junction, which in turn generates more minority carriers (due to impact ionization) flowing back toward the p+ guard ring to raise the adjacent pwell potential. Therefore, the adjacent source region is also turned into a forward bias state. With this cascading effect, the entire gate finger turns on into a snap back condition.
Prior art MOSFET-based I/O (Input/Output) structures with self-ESD protection typically including a number of NMOSFET and PMOSFET transistors. As shown in FIGS. 2A and 2B, the pull-down NMOSFET may comprises a number of gate elements, with some connected to a first gate signal for the output transistor portion, and some connected to the VSS bus/Ground as the input protection ESD structure. Similarly, the pull-up PMOSFET may comprise a number of gate elements, with some connected to a second gate signal for the output transistor portion, and some connected to the VDD bus as the input protection ESD structure. In the prior-art methods, a gate element formed of a polysilicon element is typically either coupling to a gate signal or to a power bus.
FIG. 3A shows the pull-down portion of a well known voltage-tolerant I/O and ESD protection circuit. As an example, VDD is at 3.3V and the NMOS gate oxide can withstand only up to 3.6V. But based on a stack-gate configuration, the voltages across each gate oxides of pull-down NMOS-transistors does not exceed 3.3V, even though a 5-volt signal appears at the pad. This is known as a 5V-tolerant design based on a 3.3V MOS transistors. However, the ESD performance of such 5V tolerant I/O circuit are typically not satisfactory due to shorter contact to gate spacing and larger drain-to-source spacing (less efficient bipolar for ESD snap-back mechanism). FIG. 3B shows an exampled layout for a stack-gate configuration for a (pull-down) I/O circuit.
FIG. 4A shows another ESD protection device known as a field device, or a lateral bipolar device. And FIG. 4B shows an exampled layout of a field device, with a channel region formed under a field oxide stripe for separating an n+ source regions. A filed device is a viable option as a primary ESD protection device, a minor drawback is that the trigger voltage is typically a little bit higher than a GGNMOS (Ground-Gate NMOS) or a GCNMOS (Gate-Couple NMOS) transistor.